1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method for correcting a layout pattern to meet the specification of the fabrication of reticles.
2. Description of the Prior Art
Photolithography and etching technologies are frequently used in semiconductor manufacturing. The photolithography technology usually involves transferring a complicated integrated circuit pattern to a semiconductor wafer surface for steps such as etching and implantation. These patterns must be extremely accurate for forming delicate integrated circuits so as to align with the patterns of the previous and following steps. In the photolithographic step, deviations occur and jeopardize the performance of the semiconductor device when the patterns on the reticles are transferred onto the wafer surface. Such deviations are usually related with the characters of the patterns to be transferred, the topology of the wafer and various process parameters.
There are many known verifications, corrections and compensations for the deviations caused by the optical proximity effect, process rules (PRC) and lithography rules (LRC) to improve the image quality after transfer. Some of the known methods are called optical proximity correction (OPC), process rule check (PRC) and lithography rule check (LRC). The commercial available OPC software may test problems such as pinch, bridge, and critical dimension uniformity in the layout patterns. Such methods not only test problems in the layout patterns but also correct the layout patterns on the reticles using the theoretical image. If the corrected image patterns are useable, they are output for the fabrication of reticles to obtain the correct image patterns on the wafer.
However, the above-mentioned verifications, corrections and compensations only take the problems of the layout pattern itself into consideration rather than the critical dimension error up to several nm during the fabrication of reticles. In other words, the above operations are based on the assumption that the corrected image patterns would be perfectly transferred during the fabrication of reticles. As a matter of fact, it is currently impossible. In particular, the corrected image patterns frequently barely pass the above operations, and almost no process window is left to the fabrication of reticles. Accordingly, problems still occur on the layout patterns formed by the photolithography and etching steps through the reticles. FIG. 9 illustrates the patterns formed by the transfer of the layout patterns after the optical proximity correction. In FIG. 9, a pair of separate and similar main features 910/920 is respectively illustrated. However, because the main features 910/920 each include the deviations originated from the fabrication of reticles, the main feature 920 includes a defect of bridge although the main features 910/920 are similar.
Last but not least, currently there is no available model for the verifications, corrections and compensations of the errors occurred during the fabrication of reticles.
The quality of the layout pattern is embodied by the film pattern after photolithography and etching. However, simulation of the patterns after fabrication to verify the layout pattern of the reticles has never been brought forward. Currently, the defects of the layout pattern on the reticles are corrected manually one by one, which is inconvenient and not user-friendly.
Hence, there is still a need of a better method for correcting a layout pattern to meet the specification of the fabrication of reticles, and further a method for constructing an optical proximity correction model. Such model may applied in the optical proximity correction and a layout pattern which is qualified for fabricating a reticle can be obtained to ensure a more precise transfer of layout patterns.